1. Field of the Invention
This invention relates to current mode logic (CML) circuits, and particularly to a CML delay cell with linear rail-to-rail tuning range and constant output swing.
2. Description of Background
Delay cells in current mode logic (CML) technology are frequently used in high-speed ring oscillators for phase locked loop (PLL) circuits or in delay locked loops. A typical delay cell includes a tail current source I0, a differential transistor pair M1, M2 and a variable RC-load, with the variable load capacitances implemented by PMOS load transistors. The RC-load determines the delay cell's time constant τ. In a PLL application τ is inverse proportional to the oscillation frequency given as fosc=½Nτ and in a DLL application τ corresponds to the desired delay of the input signal, where N denotes the number of delay cell stages. Ideally τ gets changed only by a variation of the load capacitance and not by a variation of the load resistor because the output common mode level is determined by VDD−R·I0/2. A variation of R would result in an undesired variation of the delay cell's common mode levels, which results in a shift of the circuit's quiescent points. When implementing the CML delay cell on transistor-level, a variation of R is virtually inevitable because the output conductance gds of the PMOS transistor used as variable C also gets affected by a variation of τ. However in the case of using PMOS load transistors, the load resistance successively decreases the more the transistor is turned on and the smaller the delay constant τ becomes. On the other hand, the load resistance and capacitance remain unchanged when the tuning voltage is below the PMOS transistor's threshold voltage (Vtune between 0.7V to 10V=Vdd). As a consequence of the non-constant load resistance above the threshold voltage of the PMOS load transistor, the output common mode voltage increases with decreasing load capacitance. This undesired behavior can be partially eliminated by increasing the tail current I0 depending on the load's nonlinearity. For instance when using an output common mode regulation scheme such as the replica biasing scheme, the output common mode is held constant if the load resistance changes as the replica biasing control adjusts the gate bias of the tail current source correspondingly. The tail current increases as much as the load resistance decreases. This compensation or common mode regulation works fine in the middle of the tuning range. However at the upper limit where Vtune approaches the PMOS threshold voltage and at the lower limit towards Vtune<20% of Vdd where the linear range of the replica biasing control ends, the compensation does not work very well. Exactly in these two ranges the compensation method proposed by adding additional switched current sources comes into play.
The principle of operation outlined above used for the linearization of a delay cell with PMOS load transistors can be applied analogously for the linearization of delay cells with NMOS load transistors. The polarities and devices types explained above then change correspondingly.